FIG. 1 illustrates two components 105 and 110 which communicate via a Peripheral Component Interface Express (PCIe) bus 115. Each component 105 and 110 includes a bus interface 120. Bus interface 120 includes a physical layer 125, such as drivers, transmitters, receivers, input buffers and other circuits to support the PCIe bus 115. PCIe is a packet-based bus protocol. Data packets are formed in the transaction layer 135 and the data link layer 130. The operation of the physical layer 125, data link layer 130, and transaction layer 135 are described in section 1.5 of the PCI Express Base Specification Revision 1.1 (March 2005) published by PCI-SIG, the contents of which are hereby incorporated by reference. A higher data rate (second generation) version of PCIe having twice the data rate of first generation PCIe is described in the draft standard PCI Express 2.0 Base Specification.
The PCIe standard specifies that a PCIe link between components must have at least one lane 140, where each lane includes a set of differential pairs having one pair for transmission (Tx) and another pair for reception (Rx). That is, each lane has dual simplex connections in that each lane has one simplex connection to transmit data to the other side of the link and one simplex connection to receive data from the other side of the link.
A PCIe bus interface 120 may include more than one transmitter/receiver pair. The PCIe standard allows for two or more lanes 140 to be aggregated to increase the bandwidth. A link training and status state machine (LTSSM) configures a set of data lanes as a link. A link between two components that aggregates a total of N lanes is described as a “by-N” link. A first generation of PCIe (“gen1”) by-N link has a bandwidth of 2.5×N Gbps in both the upstream and downstream directions. The second generation of PCIe (“gen2”) has a ×N link with twice the bandwidth, or 5×N Gbps in both upstream and downstream directions.
As illustrated in FIG. 2, a conventional ×N link between two components can also be pictured as being equivalent to two unidirectional data links 210 and 220 between the components to send and receive packets in two different directions. That is, a PCIe×N link has N lanes, which corresponds to a total of N simplex connections in one direction and N simplex directions in the other direction. PCIe permits ×1, ×2, ×4, ×8, ×12, ×16, and ×32 lane widths. As an illustrative example, in first generation PCIe, a single lane has 2.5 Gigabits/second/Lane/direction of raw bandwidth such that a ×8 link has 20 Gigabits/second of raw bandwidth in each direction.
One problem associated with conventional PCIe is that traffic between two components is variable. For example, the average traffic load may vary over time. Since a PCIe bus consumes a significant amount of power which increases with the number of active data lanes, the bus size is often a compromise between power and performance. As described in U.S. patent Ser. Nos. 10/431,994 and 11/229,208 by the assignee of the present invention, one solution to variable traffic is to adaptively vary the number of data lanes up or down depending upon such parameters as whether a power-saving mode is used or whether a high-performance mode is used. Data lanes that are unused may be placed in a low power consumption state, thereby reducing bus power consumption. The contents of U.S. patent Ser. Nos. 10/431,994 and 11/229,208 are hereby incorporated by reference.
However, the bus traffic between two components may also be highly asymmetric during certain time intervals. For example, if one component 105 utilizes a PCIe bus to send a command requesting large amounts of data from the other component 110, there is an inherent asymmetry in traffic between the upstream command requests and the downstream flow of large amounts of data. Large asymmetries in bus traffic make it difficult to simultaneously optimize power consumption and performance. In particular, in a system in which there are large time-varying asymmetries in traffic the PCIe lane width may have to be kept large enough to support the worst case peak bursts of traffic in one direction even though traffic in another direction may be light over extended periods of time.
In light of the above-described problems the apparatus, system, and method of the present invention was developed.